The present invention relates to the manufacturing of integrated circuits. More particularly, the invention relates to integrated circuits including a memory matrix manufactured by means of a process featuring self-aligned source formation and junction salicidation. Still more particularly, the invention concerns the integration in such integrated circuits of resistors and ESD (electro static discharge) protection elements.
Protection against ESD is a key issue in integrated circuits, and it is especially important in MOS integrated circuits such as memories.
MOS transistors with abrupt profile source/drain junctions are known to have a higher ESD ruggedness than LDD (lightly-doped drain) transistors. A possible explanation of this is that in an abrupt junction MOS transistor, the associated parasitic bipolar transistor that turns on by snap-back when a high-current ESD surge is applied has a deeper conduction (lower current density for a given dissipated power) than in the case of an LDD transistor.
On the other hand, it is also known that transistors having abrupt profile source/drain junctions are generally not used as elements of a logic circuitry (e.g., logic gates) in an integrated device. Such transistors are in fact affected by problems of hot-electron injection into the gate oxide. Injection of hot electrons into the gate oxide causes changes in the electrical parameters of the transistors. These problems are instead avoided using LDD transistors.
The problems of hot-electron injection become however less significant the longer the transistors"" channel. However, the use of long-channel transistors is normally avoided in the logic circuitry.
On the contrary, output buffers having a long-channel transistor is not a real limitation, especially for the pull-down part. Output buffers, being directly connected to input/output (I/O) pads, can experience electro static discharges, so the use of long-channel, abrupt junction profile transistors for output buffers is a possible way to obtain ESD self-protect output buffers.
Using a self-protected structure has the advantage that no additional, dedicated ESD protection circuitry is to be provided. This reduces the size of the I/O cells. Also, when a dedicated ESD protection structure is used, further elements such as resistors are to be provided to limit the current drawn by the protected circuitry in favor of the protection circuitry. In the case of output buffers, this means that resistors are normally placed in series with the pull-down transistors in order to limit the surge current flowing therethrough, in favor of the ESD protection circuitry. The drawback is that in normal operation the switching time of the output buffer is negatively affected.
A self-protected transistor must however comply with some layout rules that are typical of protection structures. Considering the high current value of an ESD surge, such a current must be distributed along the whole transistor width. Typically, the source/drain contacts are kept significantly distant from the transistor""s gate so to introduce a local resistance (ballast resistor) that prevents current crowding.
The integration of ESD self-protected transistors as described above is not straightforward in integrated circuits of the current generation. The following technological innovations are to be kept into suitable account.
On the one hand, current manufacturing processes for integrated circuits with a memory matrix provide for the formation of self-aligned source (SAS) diffusion lines inside the matrix of memory cells. First, field oxide strips are formed in the memory matrix area, the field oxide strips separated by active area strips; then, word lines perpendicular to the field oxide strips are defined; a selective etching of the field oxide strips is then provided, so as to remove field oxide portions among alternate pairs of word lines and thus form strips of uncovered substrate where source diffusion lines will be formed; subsequently, a dopant such as As is implanted in a heavy dose (approximately 1015 atoms/cm2) to form the source diffusion lines at the strips of uncovered substrate. The SAS technique allows for high integration densities. In some cases, depending on the desired performance of the memory cells, an additional implant of phosphorus of lower dose (1014 atoms/cm2) can be provided, so to have source junctions with more gradual profile.
Another improvement in the manufacturing processes of the current generation is junction salicidation. This technique, which provides for a substantial reduction of the resistivity of the doped regions, is essential in order to improve high-frequency performance of the devices. Salicidation provides for depositing over the doped regions a layer of a transition metal, typically Ti; the layer of transition metal is then thermally activated to form a low-resistivity layer (salicide, e.g., TiSi2) over the doped regions.
Both the SAS and the salicidation techniques are commonly employed in the manufacturing of integrated circuits.
Normally, a dedicated mask is provided to avoid salicidation of some of the doped regions in the integrated circuit. For example, low doped regions such as these lightly-doped source/drain portions of LDD transistors must not be affected by salicidation, otherwise this lightly-doped, rather shallow regions could easily be totally consumed during formation of the salicide. Another case where salicidation is to be avoided is over some N+ doped regions that are to be used to form diffused resistors with resistivity of the order of 50 xcexa9/square meter. Integrated resistors of this type are very useful in integrated circuits: firstly, they have a lower resistivity than that of resistors obtainable from lightly-doped Nxe2x88x92 regions (2000 xcexa9/square meter) and from N type wells (1000 xcexa9/square meter); secondly, resistors formed from N+ regions have a linear behavior against voltage. Resistors of this kind are for example used as ballast resistors in ESD protection structures.
The present invention provides a method that, in the context of a standard manufacturing process for integrated circuits with memory matrixes providing for a SAS masked etch and implant and junction salicidation, is suitable for obtaining doped regions that can be used to form integrated resistors with linear behavior and/or abrupt-profile source/drain regions for ESD self-protected transistors.
The foregoing is achieved by means of a method of forming a doped region in an integrated circuit which includes a matrix of memory cells and lightly-doped drain (LDD) transistors and which is fabricated by means of a process providing for a self-aligned source (SAS) masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. Further included is:
the doped region formed by introducing into a semiconductor layer of a first conductivity type a dopant of a second conductivity type, exploiting the SAS masked implant used to form source regions of the matrix of memory cells; and
at least a portion of a surface of the doped region is prevented from being salicidated by using as a protective mask a portion of a dielectric layer from which insulating sidewall spacers for the LDD transistors are formed.
The method of the present invention has the advantage of allowing the formation of a doped region that can be used both as an integrated resistor and as an abrupt-profile source/drain region for an ESD self-protected transistor, without any additional step compared to a standard manufacturing process of the current generation for integrated circuits including memory matrixes. Using the doped region formed by means of the method according to the present invention as a drain/source region for ESD self-protected transistors avoids the necessity of fulfilling particular layout rules as described above, since such a doped region not only gives rise to an abrupt-profile source/drain junction, but it also intrinsically includes a ballast resistor. For example, there is no more the necessity to have source/drain contacts spaced apart from the gate of the transistor.